The reliance on digital-to-analog converters DACs has increased multifold as digital technology has permeated the electronics industry. Due to the ever increasing demand for higher performance electronics applications, a need exists for an accurate high-speed DAC.
A conventional DAC implementation employs a long resistor string (e.g., 2.sup.n resistors) coupled in series between an upper and lower reference voltage. A n-by-2.sup.n decoder receives an n-bit digital input signal, and decodes it to select one of the 2.sup.n output lines. Each successive one of the 2.sup.n output lines is connected across each successive one of the 2.sup.n resistors of the resistor string. The voltage level seen across the selected output line of the multiplexer and the lower reference voltage is thus represented by m/2.sup.n -1, where m is the digital input value ranging from 0 to 2.sup.n -1. The analog output voltage is measured between the upper node of the m.sup.th R-bit resistor in the resistor string and the lower reference voltage.
Devices which employ more than one resistor-string based DAC coupled in parallel are problematic. First, DACs rely on the values of their circuit components, typically resistors or capacitors, to form ratios that digitally represent the ratio of an input signal to a reference signal. As a result, the primary limitation on the accuracy that can be achieved in a multi-stage DAC device is the variation in the values of the individual DAC components. This variation, known as component mismatch, causes these ratios to deviate from their nominal values, which, in turn, produces errors in the analog representation of the output signal.
Second, the string of resistors limits the charging and discharging of the parasitic capacitances associated with the nodes positioned near the middle of the resistor string. Due to the parasitic capacitance of the device, a certain amount of time is required to charge and discharge the parasitic capacitances associated with the internal nodes of the DAC. The amount of charge/discharge time is greatest for those R-bit resistors positioned close to the middle of the resistor string. In particular, for an 8-bit DAC, the worst case scenario occurs in the 256-resistor string around those resistors positioned near R-bit resistor 127 and R-bit resistor 128 in the string. The DAC output settling time when converting input digital codes having a value close to 2.sup.n /2 is increased due to this effect.
Accordingly, a need exists for a method of improving the INL component mismatching in multi-stage parallel resistor-string based DAC devices. In addition, a need exists for a method of improving the charge/discharge time of the parasitic capacitances associated with middle nodes of the resistor string.